This invention relates to interrupt handlers and methods for handling interrupts. More particularly, this invention relates to interrupt handlers with prioritized interrupt vector generators that enable configuration of interrupt type and priority among the interrupts.
An xe2x80x9cinterruptxe2x80x9d is a request-for-attention signal that is passed to a computer""s CPU (central processing unit) from hardware or software sources in an attempt to gain the CPU""s attention. Interrupts can occur for many reasons, ranging from normal to highly abnormal situations, including service requests from hardware, errors in processing, program attempts to do the impossible, and memory problems. A hardware interrupt is a request for service generated by hardware components, such as a keyboard, mouse, disk drive, I/O port, and microprocessor.
The interrupt causes the CPU to suspend its current operations, save the status of its work, and transfer control to a process for handling the interrupt. Interrupt handlers are commonly implemented in software and more particularly, in a hardware abstraction layer. The interrupt handler typically resides in the CPU at a known address. When an interrupt occurs, the CPU begins executing code at that location. The interrupt handler determines the cause of the interrupt and then services it by calling an appropriate set of instructions to be carried out.
The interrupt handler initiates different instructions for different types of interrupts. More specifically, each type of interrupt has an associated dedicated routine, known as an xe2x80x9cinterrupt service routinexe2x80x9d or xe2x80x9cISRxe2x80x9d. When a CPU receives interrupt requests from more than one source, the interrupt handler invokes a hierarchy of permission levels, called xe2x80x9cinterrupt prioritiesxe2x80x9d, to determine which of the interrupts is handled first.
Conventional software-based interrupt handlers have a drawback in that the speed and performance is often unacceptable in real-time operating systems that are required to execute interrupts at very high speed and efficiency. The performance factor is further complicated by the desire to handle prioritized sets of interrupts from many diverse hardware platforms. Different hardware platforms often have different interrupts and dissimilar interrupt priorities. To be acceptable, an interrupt handler should provide real-time response for hardware interrupts and dynamic setting of interrupt priorities.
One prior art interrupt handler that addresses these issues is described in U.S. Pat. No. 5,594,905, entitled xe2x80x9cException Handler and Method for Handling Interruptsxe2x80x9d, which issued Jan. 14, 1997 in the name of Amit Mital, and is assigned to Microsoft Corporation.
While this interrupt handler proved effective, the inventors sought to develop an even faster, hardware-based interrupt handler that minimizes software overhead to thereby improve performance.
This invention concerns an interrupt handler implemented in hardware and external to a processor to handle interrupts destined for the processor. The interrupt handler has a programmable prioritized interrupt array with programmable registers that identify priority levels and handling processes for handling one or more interrupts. The interrupt handler also has an interrupt scanning state machine that scans the prioritized interrupt array following receipt of an interrupt to extract the priority level and handling process associated with the interrupt. The interrupt handler is designed to handle interrupts in significantly less time than software implementations, thereby making the handler favorable for real time systems.
According to one implementation, the prioritized interrupt array has three registers that coordinate data associated with the interrupts received by the interrupt handler. A mask register holds mask values for corresponding interrupts that indicate whether the interrupts are enabled. A priority register holds priority levels for the various interrupts, whereby two or more interrupts may be assigned the same priority level. An address register holds information for servicing the interrupts, such as addresses for interrupt service routines. The priority register and address register are programmable to enable a user to change the priority levels and servicing information for any given interrupt source.
The interrupt scanning state machine operates on the prioritized interrupt array using a three-state process that includes an idle state, a scanning state, and an interrupt selected state. The state machine remains in the idle state until the prioritized interrupt array receives one or more active interrupts that are indicated by the mask register as being enabled. When one or more active interrupts are received, the interrupt scanning state machine transitions to the scanning state to scan the priority register and identify which of the one or more active interrupts has the highest priority. When the interrupt with the highest priority is found, the interrupt scanning state machine transitions to the interrupt selected state and accesses the address register to output information for handling the active interrupt with the highest priority.
The interrupt handler is designed to be extendable. As an example, two or more handlers can be connected in a cascading arrangement where the output of one interrupt handler supplies its highest priority interrupt as one of the many interrupts to another interrupt handler.